The present invention relates to semiconductor devices and a manufacturing method thereof, and more particularly to metal oxide semiconductor (MOS) type devices having an electrode structure capable of coping with a short circuit effect and a manufacturing method thereof.
FIG. 1 shows a constitution of a conventional semiconductor device such as a complementary-MOS (CMOS) device, specifically as a CMOS inverter.
In FIG. 1, numeral 101 denotes an n-type silicon [Si (100)] substrate, and a p-type well 102 is formed in the substrate 101. An element dividing oxide layer 103 is formed upon the substrate 101 for forming on the substrate 101 and well 102 respective element regions for PMOS and NMOS and a dividing region for insulating between elements. A gate oxide layer 104 having a thickness of 100 angstrom is formed on the element regions.
A polysilicon layer having a thickness of 3000 angstrom to be a gate electrode is formed on the element region for PMOS via the gate oxide layer 104, which is made as an n.sup.+ -type by a diffusion of phosphorus (P). A first impurity layer 108 is formed in a region immediately under the polysilicon layer 105 in the substrate 101 to prevent a punch through, and a second impurity layer 107 is formed on the first impurity layer 106 at upper surface of the substrate 101 to adjust a threshold voltage value V.sub.th. First and second impurity diffusion layers 108 and 109 to be a source or a drain of PMOS-FET (field effect transistor) are formed at both sides of the first and second impurity layers 106 and 107 by an ion implantation or a diffusion of phosphorus (P) or arsenic (As).
On the other hand, a polysilicon (policrystal silicon) layer 110 having a thickness of 3,000 angstrom to be a gate electrode is formed on the element region for NMOS via the gate oxide layer 104, which is also an n.sup.+ -type by a P-diffusion. A third impurity layer 111 is formed in a region immediately under the polysilicon layer 110 in the well 102 to prevent a punch through, and a fourth impurity layer 112 is formed on the third impurity layer 111 at upper surface of the well 102 to adjust a threshold voltage value V.sub.th. Third and fourth impurity diffusion layer 113 and 114 to be a source or drain are formed at both sides of the third and fourth impurity layers 111 and 112 by an ion implantation or a diffusion of boron (B) or boron fluoride (BF.sub.2).
A silicon oxide layer 115 for a layer insulation is formed upon an entire surface of the substrate 101 by a chemical vapor deposition (CVD), and contact holes 116 are formed by a photo-etching method in the manner that the holes 116 pass through the gate oxide layer 104 and the silicon oxide layer 115 respectively from the first and fourth impurity diffusion layer 108 and 114 which will be source regions of PMOS and nMOS to the upper surface of the oxide layer 115. In the holes 116, metal wiring portions 117 are formed of an alloy of aluminum (Al) and silicon (Si) by means of a spattering method and a patterning of a photo-etching method.
A passivation layer 118 is formed the entire surface of a wiring layer consisting of the oxide layer 115 and the wiring portions 117.
However, the conventional MOSFET is in a dilemma between an improvement of a reliability and an improvement of a device characteristic, namely, between a suppression of a short channel effect and an improvement of a current driving capability, and this problem is so serious especially about pMOSFET. Here, the short channel effect means that, in a short channel MOSFET, since a depletion layer extending into a gate contributes as a depletion layer on the side of a drain electrode, the depletion layer to be used as the gate electrode decreases, thereby reducing a threshold voltage. Accordingly, if a MOSFET has a short channel structure, the threshold voltage decreases because the threshold voltage sensitively depends upon a length of the gate.
With respect to a short-channel effect, there is a problem below. Because mass of boron (B) is smaller than that of phosphorus (P) or arsenic (As) as materials of the impurity diffusion layer of pMOS, boron (B) is inserted into deeper of the substrate at implanting an ion. Moreover, since a diffusion coefficient of boron (B) is larger than that of arsenic (As), it is difficult to shallowly form a p.sup.+ -junction used in pMOSFET, thereby resulting the problem that a depth of the junction causes a short channel effect to be in serious.
With respect to a mitigation of a short channel effect, a channel type may be changed into a surface channel type, or an LDD (a lightly doped drain source) structure. However, since both configurations make the device characteristic deteriorate, there are not the best countermeasure.
Being described in more detail, when the gate electrode is formed of materials having a predetermined work function, it is possible to make a MOSFET having both of a surface channel type and a buried channel type. Namely, when the n.sup.+ -polysilicon is used as the gate electrode, the nMOSFET becomes a surface channel type and the pMOSFET becomes a buried channel type. In the buried channel type, a carrier is flowing in a portion which is different from the gate oxide layer and a boundary plane of the substrate with a short distance, thereby making the short channel effect be remarkable. Accordingly, a p.sup.+ -polysilicon is used as a pMOSFET to make it be a surface channel type, thereby mitigating a short channel effect. As being clarified from FIG. 2, the surface channel type has a threshold voltage larger than that of the buried channel type at the same length of the gate electrode. Accordingly, if the threshold voltage needs to be kept to a predetermined level, it is possible to make the gate electrode length of the surface channel type MOS shorter than that of the buried channel type MOS.
However, in the surface channel type, since the carrier flows over the boundary surface of the MOS, resistive operation by the gate oxide layer interrupts flowing of the carrier, thereby reducing a current driving capability in comparison with the buried channel type, as shown in FIG. 3. As a result, even though the surface channel type has an effect in that the channel length can be shortened, the current driving capability of the surface channel type reduces. Accordingly, it is impossible to improve an operation speed.
On the other hand, the LDD structure as shown in FIG. 4 can reduce a short channel effect.
In FIG. 4, the LDD MOS comprises a substrate 401, a gate oxide layer 402, an n.sup.+ -polysilicon layer 403 to be the gate electrode, a first impurity layer 404 for preventing a punch through, a second impurity layer 405 for adjusting a threshold voltage V.sub.th, a first p.sup.+ impurity diffusion layer 406 which will be a source region, and a second p.sup.+ impurity diffusion layer 407 which will be a drain region. In the LDD structure, the difference opposing to the constitution shown in FIG. 1 resides in that there are provided a third and fourth impurity regions 408 and 409 at every inner sides of the first and second impurity regions 408 and 407 and having a low concentration of 1E18 to 1E19 (in this example, p.sup.- -type).
Since the LDD structure can form a shallow junction by the p.sup.- -type impurity diffusion layers 408 and 409, it is possible to suppress a short channel effect.
However, since the low concentration layers such as the impurity diffusion layer 408 and 409 have the large resistance, the current driving capability is reduced, thereby resulting a formation of a MOS which is not adaptive to high-speed operation.
Even though there has been described the problems of the conventional MOSFET mainly with respect to a pMOS, an nMOS is also in a dilemma between an improvement of a current driving capability and a reduction of a short channel effect in surface and buried channel types and an LDD structure.
As described above, the conventional MOSFET is in dilemma between a suppression of a short channel effect and an improvement of a current driving capability.